An ever-growing market demand for board (second) level packages (e.g., embedded\nsystems, system-on-a-chip, etc.) poses newer challenges for its manufacturing industry in terms\nof competitive pricing, higher reliability, and overall dimensions. Such packages are encapsulated\nfor various reasons including thermal management, protection from environmental conditions\nand dust particles, and enhancing the mechanical stability. In the due course of reducing overall\nsizes and material saving, an encapsulation as thin as possible imposes its own significance.\nSuch a thin-walled conformal encapsulation serves as an added advantage by reducing the\nthermo-mechanical stresses occurring due to thermal-cyclic loading, compared to block-sized or\nthicker encapsulations. This paper assesses the encapsulation process of a board-level package\nby means of thermoset injection molding. Various aspects reviewed in this paper include the\nconception of a demonstrator, investigation of the flow simulation of the injection molding process,\nexecution of molding trials with different encapsulation thicknesses, and characterization of the\npackages. The process shows a high dependence on the substrate properties, injection molding\nprocess parameters, device mounting tolerances, and device geometry tolerances. Nevertheless,\nthe thermoset injection molding process is suitable for the encapsulation of board-level packages\nlimiting itself only with respect to the thickness of the encapsulation material, which depends on\nother external aforementioned factors.
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